Prior to the use of solid state devices in RF/microwave power circuits, the primary method of providing high-frequency amplification was through the use of vacuum tubes. In the early days of RF power technology, vacuum tubes could be designed to provide the desired power amplification given the particular frequency ranges in use. In other words, tubes could be scaled up for power amplification purposes and their corresponding frequency response would still meet the desired purpose. However, there are several undesirable characteristics of vacuum tubes. For instance, tubes are typically large in size. Tubes also generate substantial amount of heat due to high filament currents. Also, tubes are less reliable due to physical stress caused by the high heat being generated. Thus, in the early days, there was a need for a different approach to RF power technology.
The development of semiconductor devices offered a new and improved approach to RF power technology. Although the use of early semiconductor devices resulted in some improvement in the performance of RF power circuits, these devices typically did not provide adequate power amplification for some RF applications. Consequently, techniques were developed to improve the power delivery capability of these early semiconductor devices. For instance, one technique was to add more material to these devices so that they could dissipate more power. However, this adversely affected the frequency response of these devices. This tradeoff between the power delivery capability of a device and its frequency response is known as the power dissipation vs. maximum frequency (cutoff frequency) tradeoff, and is used to characterize the performance of power devices today.
Recent developments in solid state devices have resulted in RF power devices that have improved power dissipation vs. maximum frequency performance. As a result, these newly developed power devices are being used in areas where vacuum tubes typically dominated. These newly developed devices are generally manufactured using silicon-based dies. However, other materials have or can be used, including Indium Phosphate, Gallium-Arsenide, Silicon-Germanium, and potentially Silicon Carbide. Although the recent improvements in solid state devices have been substantial, device manufacturers still strive to produce higher frequency solid state devices that have higher power delivery capability with improved efficiency.
There are several techniques used today by manufacturers to improve the power dissipation vs. maximum frequency performance of power devices and circuits. These techniques include (1) increasing the horizontal cell length of the semiconductor device; (2) increasing the vertical cell length of the semiconductor device; (3) providing parallel power circuits; (4) providing sub micron structures; and (5) forming silicon devices on diamond or silicon carbide materials for improving power dissipation. Although these techniques improve the power dissipation vs. maximum frequency performance of power devices and circuits, they also have undesirable characteristics.
FIG. 1 illustrates one approach that is currently used to increase the power handling capability of RF silicon devices, i.e. increasing the horizontal length 102 of a device cell. The horizontal length 102 of a device cell is substantially orthogonal to the flow of carriers in the device. It follows that the greater the horizontal length of a cell is, the greater amount of current flow can be achieved, without increasing the current density. Thus, increasing the horizontal length of a cell improves its current flow handling capability, which results in an improved power handling performance for the cell.
One problem with this approach occurs when the horizontal length of the cell is increased to near a quarter wavelength at the operating frequency of the device. When this occurs, the power handling capability of the device no longer increases proportionally with the increase of the cell length. The reason for this is that when the horizontal length of the cell is at or near a quarter wavelength, the cell behaves like a transmission line. The transmission line behavior results in a power distribution across the cell that is not uniform. As a result, the efficiency of the cell decreases, the dissipated power increases, and the operating junction temperature of the device increases. Furthermore, these factors result in a relatively large temperature gradient across the device that adversely affects the reliability of the device.
An additional problem with increasing the horizontal length of the cell is that it becomes more difficult to achieve a desirable impedance matching for the device. Specifically, as the device increases in size, the associated transmission line in the output circuit that collects the amplified waves, sets up a voltage standing wave ratio (VSWR) that can cause parasitic oscillations and/or catastrophic burn out. For example, if the impedance matching is such that a 1.5:1 VSWR results in wide band applications, it is very likely that spurious oscillations will be generated. Spurious outputs are undesirable in many applications. For instance, spurious oscillations can be especially harmful in radar applications due to the high power of radar pulses. These radar-associated spurious oscillations, commonly referred to as "pulse break up", can disturb the broadcast envelope of high frequency pulses and render radar components, such as amplifiers, useless for its desired applications. For such reason and others, the Federal Communications Commission (FCC) places strict limitations on the broadcast envelope of radar pulses.
As seen in FIG. 1, the problem of the horizontal cell length approaching a quarter wavelength is not only present when there is a single cell, but also when a plurality of cells are combined in a parallel relationship. FIG. 1 illustrates a parallel arrangement of three silicon cells 104, 106 and 108. The cells 104, 106 and 108 are horizontally arranged. Similar quarter wavelength problems occur when the combined horizontal length of the cells 104, 106 and 108 approach a quarter wavelength at the operating frequency of the devices. As previously stated, this can result in the formation of undesirable spurious oscillations.
FIG. 2 illustrates another approach that is currently used to increase the power handling capability of RF silicon devices, i.e. increasing the vertical length 202 of a device cell. Increasing the vertical length of a cell, just as with increasing the cell horizontal width, can produce RF power devices with increased capability. However, increasing the vertical length beyond a certain electrical length also has diminishing returns. One reason for this is that when the vertical length of the cell is increased, the amplified wave emerging from the bottom end of the cell is typically out of phase with the amplified wave emerging from the top of the cell. This phase differential decreases the summed power of the out of synchronous wave resulting in a lowering of the efficiency of the device. Typically, this occurs when the vertical length of the cell approaches three (3) degrees with respect to the wavelength of the operating frequency. When cells are horizontally arranged and their vertical lengths have been increased, there may exist two potential problems, i.e. the problem associated with the horizontal electrical length of the cell approaching a quarter wavelength, and the problem associated with the vertical electrical length approaching three (3) degrees. As seen in FIG. 1, a parallel arrangement of three vertical cells 204, 206, 208, and 210. The cells 204, 206, 208, and 210 are horizontally arranged. Similar quarter wavelength problems occur when the combined horizontal length of the cells 204, 206, 208, and 210 approach a quarter wavelength at the operating frequency of the devices. As previously stated, this can result in the formation of undesirable spurious oscillations.
Because of the aforementioned design restrictions on the horizontal and vertical lengths of a cell, some manufacturers offer "fragile" devices. A device is "fragile" if its vertical and horizontal lengths are near the upper operating limits, as previously discussed. They are characterized by having marginal stability, i.e. they can survive a maximum load mismatch of 1.15:1 VSWR. Examples of fragile RF devices can be found among commercial devices that operate in the S band frequency region, i.e. between two (2) to four (4) GHz. Commonly, commercial S band devices have efficiencies in low 40 percent range, and maximum power levels below 150 Watts.
Yet another approach that is currently used to increase the power handling capability of RF power circuits is to use parallel techniques. The basic principle behind parallel techniques is to divide input signal among several devices, and then re-combine the amplified signals produced by them. One common parallel method is the "Wilkinson" method. The Wilkinson method employs distributed microstrip technologies to divide the input signal into a plurality of input signals. The resulting input signals are then applied to respective devices for amplification. The amplified signals are then re-combined to form a higher power output signal.
There are several problems with parallel techniques. One is that they typically require a substantial amount of real estate to implement. Another problem is that there is little difference between employing parallel techniques and simply using discrete transistors. If such is the case, manufacturers may just as well form their power circuits by combining discrete transistors, instead of using integrated devices. Thus, employing parallel techniques may not be a feasible solution.
An additional approach that is currently used to increase the power handling capability of RF power devices is to use sub micron structures. Sub micron structures can increase the effective device area, thereby causing an increase in the current injected within the device. As a result, devices having sub micron structures typically have improved power handling capability. However, sub micron structure are generally difficult to manufacture, and require an expensive, state-of-the-art wafer fabrication facility. Thus, because of the difficulty and expense of manufacturing RF devices with sub micron structures, they are not widely used for most applications.
FIG. 3 illustrates a further approach that is currently used to increase the power handling capability of RF power circuits and devices, i.e. the use of silicon on diamond techniques. Silicon on diamond technique comprises mounting a silicon device 302 on a diamond carrier 304. Because diamond is a highly efficient conductor of heat, a diamond substrate 304 acts as a heat sink and heat spreader, and allows more power to be extracted from a semiconductor device during operation of the device. This results in the semiconductor device operating under cooler temperature conditions, which improves the power handling capability of the device.
Research in this area has not yet produced economically viable products. Diamond packages, such as shown in FIG. 3, are several times more expensive than Beryllium-oxide (BeO) packages, another known heat conductor. BeO is also characterized by having low electrical conductivity, which makes it advantageous in certain applications requiring electrical insulation and heat dissipation. In addition, BeO can be significantly less expensive than diamond.
The industry has also researched other materials for use in the fabrication of high frequency power semiconductor devices. Silicon Carbide, for example, has been promising, but commercialization has been difficult. Silicon Carbide wafers, the basic building block for Silicon Carbide devices, have a tendency to contain excessive crystalline defects. As a result of excessive crystalline defects, Silicon Carbide wafers typically exhibit lower yields. Because of these manufacturing difficulties, Silicon Carbide wafers are substantially more expensive than silicon wafers.